W65C816S Datasheet, PDF (59/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
W65C816S Data Sheet
8.12 Binary Mode
The Binary Mode is set whenever a hardware or software interrupt is executed. The D flag within the Status
Register is cleared to zero.
8.13 WAI Instruction
The WAI instruction pulls RDY low and places the processor in the WAI "low power" mode. NMIB, IRQB or
RESB will terminate the WAI condition and transfer control to the interrupt handler routine. Note that an
ABORTB input will abort the WAI instruction, but will not restart the processor. When the Status Register I
flag is set (IRQB disabled) the IRQB interrupt will cause the next instruction (following the WAI instruction)
to be executed without going to the IRQB interrupt handler. This method results in the highest speed response
to an IRQB input. When an interrupt is received after an ABORTB which occurs during the WAI instruction,
the processor will return to the WAI instruction. Other than RESB (highest priority), ABORTB is the next
highest priority, followed by NMIB or IRQB interrupts.
8.14 The STP Instruction
The STP instruction disables the PHI2 clock to all internal circuitry. When disabled, the PHI2 clock is held in
the high state. In this case, the Data Bus will remain in the data transfer state and the Bank address will not be
multiplexed onto the Data Bus. Upon executing the STP instruction, the RESB signal is the only input which
can restart the processor. The processor is restarted by enabling the PHI2 clock, which occurs on the falling
edge of the RESB input. Note that the external oscillator must be stable and operating properly before RESB
goes high.
8.15 COP Signatures
Signatures 00-7F may be user defined, while signatures 80-FF are reserved for instructions on future
microprocessors. Contact WDC for software emulation of future microprocessor hardware functions.
8.16 WDM OpCode Use
The WDM OpCode may be used on future microprocessors. It performs no operation. WDM are the initials of
William D. Mensch, Jr., the founder of WDC.
8.17 RDY Pulled During Write
The NMOS 6502 does not stop during a write operation. In contrast, both the W65C02S and the W65C816S
do stop during write operations
8.18 MVN and MVP Affects on the Data Bank Register
The MVN and MVP instructions change the Data Bank Register to the value of the second byte of the
instruction (destination bank address).
The Western Design Center
W65C816S
59