W65C816S Datasheet, PDF (56/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
8 Caveats
Table 8-1 Caveats
W65C816S Data Sheet
Compatibility Issue
S (Stack)
X (X Index Reg)
Y (Y Index Reg)
A (Accumulator)
(Flag Reg)
Timing
A.ABS,X,ASL,LSR,
ROL
with no Page Crossing
B. Jump Indirect
Operand =XXFF
C. Branch Across Page
D. Decimal Mode
BRK Vector
Interrupt or Break
Bank Address
Memory Lock (ML)
Indexed Across Page
Boundary (d),y a,x
a,y
RDY Pulled during
Write Cycle
NMOS 6502
Always Page 1, 8
bits
Always Page 0
Always less than
256 ie 8 Bits
Always Page 0
Always less than
256 ie 8 Bits
8 bits
N, V and Z flags invalid
in decimal mode.
D=unknown after reset.
D not modified after
interrupt
7 cycles
5 cycles and invalid
page crossing
4 cycles
No add. cycles
FFFE,F BRK bit=0 on
stack if IRQ, NMI
Not available
Not available
Extra read of
invalid address
Ignored
W65C02
Always Page 1, 8
bits
Always Page 0
Always less than
256 ie 8 Bits
Always Page 0
Always less than
256 ie 8 Bits
8 bits
N,V and Z flags valid in
decimal mode. D=0
after reset/interrupt
6 cycles
6 cycles
4 cycles
Add 1 cycle
FFFE,F BRK bit=0 on
stack if IRQ, NMI
Not available
MLB=0 during
Modify and Write
cycles
Extra read of last
instruction fetch
Processor stops
W65C02S
Always page 1, 8
bits
Always Page 0
Always less than
256 ie 8 Bits
Always Page 0
Always less than
256 ie 8 Bits
8 bits
N,V and Z flags valid in
decimal mode. D=0
after reset /interrupt
6 cycles
6 cycles
4 cycles
Add 1 Cycle
FFFE,F BRK bit=0 on
stack if IRQ, NMI
Not available
MB=0 during
Modify and Write
cycles
Extra read of last
instruction fetch
Processor stops
W65C816S
Always page 1 8 bits
when(E=1), 16 bits
when E=0
Indexed page zero
always in page 0
(E=1), Cross page
(E=0)
Indexed page zero
always in page 0
(E=1), Cross page
(E=0)
8 bits (M=1), 16 bits
(M=0)
N,V and Z flags valid in
decimal mode. D=0 after
reset/interrupt
7 cycles
5 cycles
4 cycles
No add. cycles
00FFFE,F(E=1) BRK bit=0
on stack if IRQ- NMIB,
ABORTB
000FFE6,7 (E=0), X=X on
stack always
PBR not pushed (E=1)
RTI, PBR, not pulled
(E-1) PRB pushed (E=0)
RTI, PBR pulled (E=0)
MLB=0 during Read
Modify and Write
cycles
Extra read of invalid
address
Processor Stops
The Western Design Center
W65C816S
56