W65C816S Datasheet, PDF (7/62 Pages) List of Unclassifed Manufacturers – Microprocessor

The Western Design Center, Inc.
1 INTRODUCTION
W65C816S Data Sheet
The W65C816S is a low power cost sensitive 16-bit microprocessor. The variable length instruction set and manually
optimized core size makes the W65C816S an excellent choice for low power System-on-Chip (SoC) designs. The Verilog RTL
model is available for ASIC design flows. WDC, a Fabless Semiconductor Company, provides packaged chips for evaluation
or volume production. To aid in system development, WDC provides a Development System that includes a W65C816DB
Developer Board, an In-Circuit Emulator (ICE) and the W65cSDS Software Development System, see
www.westerndesigncenter.com for more information.
The WDC W65C816S is a fully static CMOS 16-bit microprocessor featuring software compatibility* with the 8-bit NMOS
and CMOS 6500-series predecessors. The W65C816S extends addressing to a full 16 megabytes. These devices offer the
many advantages of CMOS technology, including increased noise immunity, higher reliability, and greatly reduced power
requirements. A software switch determines whether the processor is in the 8-bit "emulation" mode, or in the native mode, thus
allowing existing systems to use the expanded features.
As shown in the W65C816S Processor Programming Model, Figure 2-2, the Accumulator, ALU, X and Y Index registers, and
Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page register augments the Direct Page addressing
mode (formerly Zero Page addressing). Separate Program Bank and Data Bank registers provide 24-bit memory addressing
with segmented or linear addressing.
Four new signals provide the system designer with many options. The ABORTB input can interrupt the currently executing
instruction without modifying internal register, thus allowing virtual memory system design. Valid Data Address (VDA) and
Valid Program Address (VPA) outputs facilitate dual cache memory by indicating whether a data segment or program segment
is accessed. Modifying a vector is made easy by monitoring the Vector Pull (VPB) output.
KEY FEATURES OF THE W65C816S
• Advanced fully static CMOS design for low power • Low power consumption (300uA@1MHz)
consumption and increased noise immunity
• Separate program and data bank registers allow
• Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%,
program segmentation or full 16 MByte linear
3.0+/- 5%, 3.3+/ - 10%, 5.0+/- 5% specified for use
addressing
with advanced low voltage peripherals
• New Direct Register and stack relative addressing
• Emulation mode allows complete hardware and
provides capability for re-entrant, re-cursive and re-
software compatibility with 6502 designs
locatable programming
• 24-bit address bus provides access to 16 MBytes of • 24 addressing modes - 13 original 6502 modes with 92
memory space
instructions using 256 OpCodes
• Full 16-bit ALU, Accumulator, Stack Pointer and • Wait-for-Interrupt (WAI) and Stop-the-Clock (STP)
Index Registers
instructions further reduce power consumption,
• Valid Data Address (VDA) and Valid Program
decrease interrupt latency and allows synchronization
Address (VPA) output for dual cache and cycle steal
with external events
DMA imple mentation
• Co-Processor (COP) instruction with associated vector
• Vector Pull (VPB) output indicates when interrupt
supports co-processor configurations, i.e., floating point
vectors are being addressed
processors
• Abort (ABORTB) input and associated vector supports • Block move ability
processor repairs of bus error conditions
*Except for the BBRx, BBSx, RMBx, and SMBx bit manipulation instructions which do not exist for the W65C816S
The Western Design Center
W65C816S
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