LM3S1620 Datasheet, PDF (61/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1620 Microcontroller
code. It can determine that it has been restarted from Hibernate mode by inspecting the
Hibernation module registers.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 61 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
Offset Name
Type
Reset
Description
0x000
0x004
0x008
0x010
0x014
0x018
0x01C
0x030
0x034
0x040
DID0
DID1
DC0
DC1
DC2
DC3
DC4
PBORCTL
LDOPCTL
SRCR0
RO
-
Device Identification 0
RO
-
Device Identification 1
RO
0x007F.003F Device Capabilities 0
RO
0x0010.70DF Device Capabilities 1
RO
0x0707.1133 Device Capabilities 2
RO
0x0F00.BFFF Device Capabilities 3
RO
0x0000.00FF Device Capabilities 4
R/W
0x0000.7FFD Brown-Out Reset Control
R/W
0x0000.0000 LDO Power Control
R/W
0x00000000 Software Reset Control 0
See
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September 02, 2007
61
Preliminary