LM3S1620 Datasheet, PDF (454/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Electrical Characteristics
21.2.3
21.2.4
Parameter Name
Value
Units
Oscillation mode
Parallel Parallel Parallel Parallel
Temperature stability (0 - 85 °C) ±25 ±25 ±25 ±25 ppm
Motional capacitance (typ)
27.8 37.0 55.6 63.5 pF
Motional inductance (typ)
14.3 19.1 28.6 32.7 mH
Equivalent series resistance (max) 120 160 200 220 Ω
Shunt capacitance (max)
10
10
10
10
pF
Load capacitance (typ)
16
16
16
16
pF
Drive level (typ)
100 100 100 100 µW
Analog Comparator
Table 21-8. Analog Comparator Characteristics
Parameter Parameter Name
Min Nom Max Unit
V_OS
V_CM
C_MRR
Input offset voltage
Input common mode voltage range
Common mode rejection ratio
- ±10 ±25 mV
0 - V_DD-1.5 V
50 -
- dB
T_RT Response time
--
1 µs
T_MC Comparator mode change to Output Valid - -
10 µs
Table 21-9. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name
Min Nom Max Unit
R_HR Resolution high range
R_LR Resolution low range
- V_DD/32 - LSB
- V_DD/24 - LSB
A_HR Absolute accuracy high range -
- ±1/2 LSB
A_LR Absolute accuracy low range -
- ±1/4 LSB
I²C
Table 21-10. I²C Characteristics
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
I1^a
t_SCH Start condition hold time
36 -
-
system clocks
I2^a
t_LP
Clock Low period
36 -
-
system clocks
I3^b
t_SRT I2CSCL/I2CSDA rise time (V_IL =0.5 V to V _IH =2.4 V) - - (see note b)
ns
I4^a
t_DH Data hold time
2-
-
system clocks
I5^c
t_SFT I2CSCL/I2CSDA fall time (V_IH =2.4 V to V _IL =0.5 V) - 9
10
ns
I6^a
t_HT Clock High time
24 -
-
system clocks
I7^a
t_DS Data setup time
18 -
-
system clocks
I8^a
t_SCSR Start condition setup time (for repeated start condition 36 -
-
system clocks
only)
I9^a
t_SCS Stop condition setup time
24 -
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
454
September 02, 2007
Preliminary