LM3S1620 Datasheet, PDF (455/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1620 Microcontroller
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 21-2. I²C Timing
I2
I6
I5
I2CSCL
I1
I4
I7
I8 I3
I9
I2CSDA
21.2.5
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 V_DC or powered down with the same regulator controlled
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 21-11. Hibernation Module Characteristics
Parameter No Parameter
Parameter Name
Min Nom Max Unit
H1
t_{HIB_LOW} Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2
t_{HIB_HIGH} Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3
t_{WAKE_ASSERT} /WAKE assertion time
62 - - μs
H4
t_WAKETOHIB /WAKE assert to /HIB desassert
H5
t_{XOSC_SETTLE} XOSC settling time^a
62 - 124 μs
20 - - ms
H6
t_{HIB_REG_WRITE} Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7
t_{HIB_TO_VDD} HIB deassert to VDD and VDD25 at minimum operational level
- - 250 μs
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 21-3. Hibernation Module Timing
32.768 KHz
(internal)
H1
H2
/HIB
H4
/WAKE
H3
September 02, 2007
455
Preliminary