LM3S1620 Datasheet, PDF (282/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10
9
8
7
6
5
4
3:0
Name
reserved
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0x00
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
282
September 02, 2007
Preliminary