LM3S1620 Datasheet, PDF (119/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1620 Microcontroller
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
7.3.4
External Wake-Up from Hibernation
The following steps are needed to use the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
7.3.5 RTC/External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
7.4 Register Map
Table 7-1 on page 119 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of t_{HIB_REG_WRITE} between write
accesses. See “Register Access Timing” on page 115.
Table 7-1. Hibernation Module Register Map
Offset Name
Type
Reset
Description
0x000 HIBRTCC
0x004 HIBRTCM0
0x008 HIBRTCM1
0x00C HIBRTCLD
0x010 HIBCTL
0x014 HIBIM
0x018 HIBRIS
0x01C HIBMIS
0x020 HIBIC
0x024 HIBRTCT
0x030-
0x12C
HIBDATA
RO
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W1C
R/W
R/W
0x0000.0000
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.7FFF
0x0000.0000
Hibernation RTC Counter
Hibernation RTC Match 0
Hibernation RTC Match 1
Hibernation RTC Load
Hibernation Control
Hibernation Interrupt Mask
Hibernation Raw Interrupt Status
Hibernation Masked Interrupt Status
Hibernation Interrupt Clear
Hibernation RTC Trim
Hibernation Data
See
page
121
122
123
124
125
127
128
129
130
131
132
September 02, 2007
119
Preliminary