LM3S1620 Datasheet, PDF (14/485 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 196
General-Purpose Timers ............................................................................................................. 197
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 209
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 210
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 212
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 214
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 217
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 219
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 220
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 221
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 223
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 224
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 225
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 226
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 227
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 228
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 229
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 230
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 231
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 232
Watchdog Timer ........................................................................................................................... 233
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 236
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 237
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 238
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 239
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 240
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 241
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 242
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 243
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 244
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 245
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 246
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 247
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 248
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 249
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 250
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 251
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 252
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 253
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 254
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 255
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 256
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 264
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 266
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 268
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 270
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 271
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 272
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September 02, 2007
Preliminary