LM3S1620 Datasheet, PDF (31/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1620 Microcontroller
1.4.6
1.4.6.1
1.4.6.2
1.4.7
1.4.7.1
1.4.7.2
Memory Peripherals
The LM3S1620 controller offers both single-cycle SRAM and single-cycle Flash memory.
SRAM (see page 133)
The LM3S1620 static random access memory (SRAM) controller supports 32 KB SRAM. The internal
SRAM of the Stellaris^® devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Flash (see page 134)
The LM3S1620 Flash controller supports 128 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
Additional Features
Memory Map (see page 39)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S1620 controller can be found in “Memory Map” on page 39. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
JTAG TAP Controller (see page 44)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
September 02, 2007
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Preliminary