QL82SD Datasheet, PDF (49/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
LVDS SERDES Internal Signals (Channel Clocks A and B)
Table 41: LVDS SERDES Internal Signals (Channel Clocks A and B)
Signal Name
Description
ClkA_rst Channel Clock A Reset Signal
ClkA_oe Channel Clock A Output Enable (1 =transmit, 0=receive)
ClkA_en Channel Clock A Enable (reduces power when set to 0)
ClkA_mode[1:0]
Channel Clock A MODE pins. See the SERDES Channel Clock Functional
Description
ClkA_txclk Channel Clock A Parallel Transmit Clock
ClkA_rxclk Channel Clock A Parallel Receive Clock
NOTE: All ClkA signals above repeat for ClkB. SERDES channel clocks A and B are
identical.
208 PQFP Pinout Diagram
Pin #1
Pin #157
Quic kSD
QL82SD-6PQ208C
Pin #53
Figure 56: QL82SD - 208PQFP Pinout Diagram
Pin #105
© 2002 QuickLogic Corporation
Preliminary
•
www.quicklogic.com
•
•
•
49
•
•