QL82SD Datasheet, PDF (18/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
SERDES Switching Characteristics - Deserializer/Receiver
Table 17: Deserializer / Receiver Switch Characteristics
CDR (10:1) Mode
Symbol
Parameter
Conditions
Min
Typ
t_RCP
t_RDC
t_DD
t_RXPD
t_DSR1
ChX_rxclk Period
ChX_rxclk Duty Cycle
Deserializer Delay
ChX_rxclk to ChX_rxd[9..0]
Deserializer PLL Lock Time
from powered-down state
28.5
Figure 23
45
2 × t_RCP + 1.5
1.5
Figure 24: 25 MHz
Figure 24: 50 MHz
T
50
2 × t_RCP + 2.5
2.5
5
8
t_DSR2
t_DJIT
Figure : 25 MHz
Deserializer PLL Lock Time from SYNCPAT
Figure : 50 MHz
Pad_ChX_p/n Jitter
25 MHz
50 MHz
1
0.75
±350
±200
Channel Link (8:1, 7:1, 4:1) Mode
Symbol
Parameter
Conditions
Min
Typ
Max
40.0
55
2 × t_RCP + 3.5
3.5
Max
Units
nS
%
nS
nS
uS
uS
uS
uS
pS
pS
Units
t_RCP
ChX_rxclk Period
Mode Dependent
LVDS Link ^-1
Frequency
Compression
Mode
Mode Dependent
LVDS Link ^-1
T
Frequency
nS
Compression
Mode
t_RDC
t_DD
ChX_rxclk Duty Cycle
Deserializer Delay
45
50
55
%
2 × t_RCP + 1.5 2 × t_RCP + 2.5 2 × t_RCP + 3.5
nS
t_RXPD
ChX_rxclk to ChX_rxd[N-1..0]
1.5
2.5
3.5
nS
t_RXDS
t_RXDH
Pad_ChX_p/n Setup to Strobe Position
Pad_ChX_p/n Hold to Strobe Position
Figure 26
150
200
pS
150
200
pS
t_SCD
Pad_ClkX_p/n to Serial Clock Delay ^a
0.6
0.8
1
nS
t_SCP
t_RXD[N-1]
Serial Clock Period
Receiver Input Strobe Position for Bit [N-1]
[N-1] × t_SCP + 1.1
T/mode
nS
[N-1] × t_SCP + 2.4 nS
t_DSR1
Deserializer PLL Lock Time from
powered-down state
Figure 24: 25 MHz
Figure 24: 50 MHz
5
8
uS
uS
t_DJIT
Pad_ChX_p/n Jitter
25 MHz
50 MHz
±300
pS
±150
pS
Asynchronous Level Conversion (1:1) Mode
t_ADD
Asynchronous Deserializer Delay -
Data Channel
1.7
nS
Figure 27
t_ADC
AsynchrCohnaonunseSl eCrlioaclizkear Delay -
0.6
0.8
1
nS
a. These values include the delay resulting from application of internal compensation for data/clock skew.
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Preliminary
© 2002 QuickLogic Corporation