QL82SD Datasheet, PDF (45/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
Programmable Logic Routing
The QL82SD device provides six types of routing resources (as in the QuickRAM devices):
short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed
networks, and defaults.
• Short wires span the length of one logic cell, always in the vertical direction. Dual wires
run horizontally and span the length of two logic cells.
NOTE: Short and dual wires are predominantly used for local connections. They
effectively traverse one or two logic cells that utilize an interconnect element to continue
to the next cell or to change direction.
• Quad wires have passive link interconnect elements every fourth logic cell. As a result,
these wires are typically used to implement intermediate or medium length fan-out nets.
• Express lines run the length of the programmable logic uninterrupted. Each of these
lines has a higher capacitance than a quad, dual or short wire, but less capacitance than
shorter wires connected to run the length of the device. The resistance will also be lower
because the express wires don't require the use of "pass" links. Express wires provide
higher performance for long routes or high fan-out nets.
• Distributed networks are described in the clock/control section. These wires span the
programmable logic, and are driven by "column clock" buffers. Each dedicated clock
network pin buffer is hard wired to a set of column clock buffers. Five global networks
"global buffers" can be connected through special purpose routing called "HSCK lines"
to either a dedicated pin buffer, or any vertical routing wire crossing it.
Global POR (Power-On Reset)
The QuickSD device features a global power-on reset. This reset will be hardwired to all
registers and will reset the registers upon power-up of the device. The circuitry used to
support the global POR is similar to the power-up loading circuitry.
VCC
Power-on
Reset
Q
0
Figure 54: Power-On Reset
Separate Power & Logic Cell Power
To decrease the logic cell area and to eliminate the need for disable transistors in the input
stage of the logic cell, a separate power supply for the logic cells has been added to the
QuickSD device. This supply will be grounded during programming and for various test
modes.
© 2002 QuickLogic Corporation
Preliminary
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