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QL82SD Datasheet, PDF (21/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps
QL82SD Device Data Sheet Rev C
Electrical Specification - Programmable Fabric
DC Characteristics
Symbol
II
IOZ
CI
IOS
ICC
ICCIO
IREF
IPD
Table 19: DC Characteristics
Parameter
Conditions
Min
I or I/O Input Leakage Current
3-State Output Leakage Current
Input Capacitance a
Output Short Circuit Current b
D.C. Supply Current c
D.C. Supply Current on VCCIO
D.C. Supply Current on VREF
Pad Pull-down (programmable)
VI = VCCIO or GND
-10
VI = VCCIO or GND
-10
Vo = GND
-15
Vo = VCC
40
VI,Vo =VCCIO or GND 0.50 (typ)
0
-10
VCCIO = 3.6 V
Max
10
10
8
-180
210
2
2
10
150
Units
µA
µA
pF
mA
mA
mA
mA
µA
µA
a. Capacitance is sample tested only. Clock pins are 12 pF maximum.
b. Only one output at a time. Duration should not exceed 30 seconds.
c. For -4/-5/-6/-7 commercial grade devices only. Maximum ICC is 3 mA for all industrial grade devices.
DC Input/Output Levels
Table 20: DC Input/Output Levels
LVTTL
LVCMOS2
GTL+
PCI
SSTL2
SSTL3
VREF
VMIN VMAX
n/a n/a
n/a n/a
0.88 1.12
n/a n/a
1.15 1.35
1.30 1.70
VIL
VIH
VOL
VOH
IOL
VMIN
VMAX
VMIN
VMAX
VMAX
VMIN
mA
-0.3
0.8
2.0
- VCCIO 0.3 0.40
2.40 2.0
-0.3
0.7
1.7
- VCCIO 0.3 0.70
1.70 2.0
- - - 0.3 VREF 2.0 VREF + 2.0 VCCIO 0.3 0.60
n/a
40
- - 0.3 0.30 × VCC 0.50 × VCC VCCIO 0.5 0.10 × VCC 0.90 × VCC 1.5
- - 0.3 VREF 0.18 VREF + 0.18 VCCIO + 0.3 0.74
1.76 7.6
- - 0.3 VREF 0.20 VREF + 2.0 VCCIO + 0.3
1.10
1.90 8.0
IOH
mA
-2.0
-2.0
n/a
-0.5
-7.6
-8.0
NOTE: The above table gives the programmable logic timing model for the QuickSD device.
The programmable logic includes the following major elements: Super Logic (Flip-Flop and
Combinational Circuit), Clock, and I/O.
© 2002 QuickLogic Corporation
Preliminary
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