QL82SD Datasheet, PDF (25/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

TIN, TINI
QL82SD Device Data Sheet Rev C
TICLK
TISU
+
-
QE
D
R
tSID
PAD
Figure 36: Input Register Cell
Table 24: Input Register Cell
Symbol
Input Register Cell Only
Parameter
Propagation
Delay (ns)
t_ISU
Input Register Setup Time: the amount of time the synchronous
input of the flip flop must be stable before the active clock edge.
3.12
t_IH
Input Register Hold Time: the amount of time the synchronous input
of the flip flop must be stable after the active clock edge.
0
t_ICLK
Input Register Clock to Q: the amount of time taken by the flip flop
to output after the active clock edge.
1.08
t_IRST
Input Register Reset Delay: the amount of time between when the
flip flop is “reset” (low) and when Q is consequently “reset” (low).
0.99
t_IESU
Input Register Clock Enable Setup Time: the amount of time
“enable” must be stable before the active clock edge.
0.37
t_IEH
Input Register Clock Enable Hold Time: the amount of time “enable”
must be stable after the active clock edge.
0
© 2002 QuickLogic Corporation
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