QL82SD Datasheet, PDF (31/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
LVDS SERDES Data Channel Configuration
A representation of the SERDES data channel is shown in Figure 43. The device consists of
eight identical data channels.
Ch0_rst
Ch0_oe
Ch0_en
Ch0_pre_emp
Ch0_sync
Ch0_mode[3:0]
Ch0_txd[9:0]
Ch0_txclk
SERDES
Channel 0
Ch0_lock
Ch0_rxd[9:0]
Ch0_rxclk
pad_Ch0-p
pad_Ch0_n
Figure 43: SERDES Channel 0
Each SERDES data channel can be operated independently. The data channels are
transceivers, so they can either send or receive data on the serial LVDS wire pair. The
direction of transfer is selected with the ChX_oe pin. If this pin is high, the channel is in
transmit mode, if this pin is low, the channel is in receive mode.
The data channel can be configured to deal with different parallel data widths and clocking
mechanisms, Table 29 shows the settings for the ChX_mode[3:0] pins and the modes that
they refer to.
For the Channel Clock A/B modes, see “LVDS SERDES Channel Clock Configuration” on
page 32 for more details. If the data channel is not needed, then it can be powered down (to
reduce overall device power) by tying the ChX_en signal low. This signal must be held high
for normal operation.
For a detailed description of how to use the various modes of the data channel to transmit
and receive data, see “LVDS SERDES Transmit and Receive Operation” on page 33.
ChX_mode[3]
Table 29: ChX_mode[3:0]
Description
Low Frequency (1), High Frequency (0)
bit [3]
bit [2]
bit [1]
bit [0]
Determines high or low frequency lock range for internal SERDES PLL.
When this bit is set to ‘1’, the low frequency range is selected.
When this bit is set to ‘0’, the high frequency range is selected.
In 10:1 mode, this bit must be set to ‘0’.
In channel clock mode, the pin setting does not matter.
Embedded clock mode (0), channel-clock (1)
CLKA (1), CLKB (0) channel clock select
© 2002 QuickLogic Corporation
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