QL82SD Datasheet, PDF (28/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
RAM Cell Synchronous Write Timing
Table 27: RAM Cell Synchronous Write Timing
Symbol
Parameter
t_SWA
t_HWA
t_SWD
t_HWD
t_SWE
t_HWE
t_WCRD
WA setup time to WCLK: the amount of time the WRITE ADDRESS
must be stable before the active edge of the WRITE CLOCK
WA hold time to WCLK: the amount of time the WRITE ADDRESS
must be stable after the active edge of the WRITE CLOCK
WD setup time to WCLK: the amount of time the WRITE DATA must
be stable before the active edge of the WRITE CLOCK
WD hold time to WCLK: the amount of time the WRITE DATA must
be stable after the active edge of the WRITE CLOCK
WE setup time to WCLK: the amount of time the WRITE ENABLE
must be stable before the active edge of the WRITE CLOCK
WE hold time to WCLK: the amount of time the WRITE ENABLE must
be stable after the active edge of the WRITE CLOCK
WCLK to RD (WA=RA): the amount of time between the active WRITE
CLOCK edge and the time when the data is available at RD
Propagation
delay (ns)
0.675
0
0.654
0
0.623
0
4.38
WCLK
WA
tSWA
tHWA
WD
tSWD
tHWD
WE
tSWE
tHWE
RD
old data
new data
tWCRD
Figure 41: RAM Cell Synchronous Write Timing
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Preliminary
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