QL82SD Datasheet, PDF (35/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
• t_SCD is the delay between the rising edge of the LVDS channel clock and the first rising
edge of the multiplied internal serial clock corresponding to the same data frame.
• t_RXD[N-1] is the internal clock strobe positions with respect to the rising edge of the LVDS
channel clock
NOTE: t_RXD[N-1] denotes physical strobe positions with respect to pad ClkX_p/n while
pad_ChX_p/n bit[n] refers to logical bit positions with respect to ChX_rxd[7:0]
Asynchronous Level Conversion Mode for the Data Channel and
Channel Clock
When the SERDES data channel ChX_mode[3:0] pins are set to use a channel clock which
is in level translator mode, then that data channel is also in level translator mode. In level
translator mode, the data channel only converts the internal CMOS signal to LVDS (for
output mode), or vice versa for input mode.
When the data channel or channel clock is in this asynchronous signal translation mode, and
configured as outputs (ChX_oe or ClkX_oe high) the output mode waveforms in Figure 22
apply.
When the data channel or channel clock is in this asynchronous signal translation mode, and
configured as inputs (ChX_oe or ClkX_oe low) the input mode waveforms in Figure 27 apply.
Programmable Fabric Description
The QuickSD device features an enhanced Super Logic Cell with an additional D flip-flop
register and associated control logic. This advanced architectural approach addresses today's
highly register intensive designs.
The QuickSD logic Supercell structure, shown in Figure 45, is similar to the .35 mm
QuickLogic logic cell with the addition of a second register. Both registers share CLK, SET
and RESET inputs. The second register has a two-to-one multiplexer controlling its input.
This register can be loaded from the NZ output or directly from a dedicated input.
NOTE: The input "PP" is not an "input" in the classical sense. It can only be tied high or low
using default links only and is used to select which path "NZ" or "PS" is used as an input to
the register. All other inputs can be connected not only to "tiehi" and "tielo" but to multiple
routing channels as well.
The complete logic cell consists of two 6-input AND gates, four two-input AND gates, seven
two-to-one multiplexers, and two D flip-flops with asynchronous SET and RESET controls.
The cell has a fan-in of 30 (including register control lines) and fits a wide range of functions
with up to 17 simultaneous inputs. It has six outputs, of which four are combinatorial and
two are registered. The high logic capacity and fan-in of the logic cell accommodate many
user functions with a single level of logic delay while other architectures require two or more
levels of delay.
© 2002 QuickLogic Corporation
Preliminary
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