QL82SD Datasheet, PDF (14/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
SERDES Timing Requirements
NOTE: Both Table 14 and Table 15 refer to CDR (10:1) Mode for ChX_txclk and
Channel Link (8:1, 7:1, 4:1) Mode for ClkX_txclk
Table 14: Serializer / Transmitter Transmit Clock
Symbol
Parameter
Conditions Min Typ Max Units
t_TCP
Transmit Clock Period
Mode
Dependent
n/a
T
n/a
nS
t_TDC
t_CLKT
t_JIT
Transmit Clock Duty Cycle
Transmit Clock Input Transition Time
Transmit Clock Input Jitter
Figure 17
45
50
55
%
1
n/a n/a V/nS
n/a
n/a
150.0
pS
(RMS)
Symbol
t_RFCP
t_RFDC
t_RFCP/t_TCP
t_RFTT
Table 15: Deserializer / Receiver Transmit Clock
Parameter
Conditions Min Typ Max Units
Reference Clock Period
Mode
Dependent
n/a
T
n/a
nS
Reference Clock Duty Cycle
40
50
60
%
Ratio of Reference Clock to
Transmit Clock
0.4 0.5 0.6
n/a
Reference Clock Transition Time
Figure 17
1
n/a n/a V/nS
90%
txclk ^10%
90%
10%
tclkT/tRFTT
tclkT/tRFTT
Figure 17: Serializer Transmit Clock / Deserializer Reference Clock Transition Times
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Preliminary
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