82C881 Datasheet, PDF (46/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
10.2.2 Implementation
For Debugging, the chip has to be in debug mode. For this, bit 5 in miscReg of ohciRegVebdor.v is defined. It has to be
asserted in order for the chip to be in debug mode.
Base Address Register 5 is assigned to be used for mapping the FIFOs. The identification of this base address Register is to
be done during PCI configuration cycle. The address bit [31:6] is used for assigning the memory. Address bit [5:0] is for
selecting the FIFO. Base address Reg 5 is memory mapped in the PCI Address space.
10.2.2.1 Writing onto Tx FIFO
For writing into the Tx FIFO, a PCI write cycle has to be started in the debug mode. It will generate a signal called
"FIFOWrAcc_c" and assert the correct "grantType" on the "targetAddr" line, to which "noBurst" and "targetReady" will be
generated to PCI. Seeing this, it will give the data validated by "targetValidData" signal. "targetValidData" will be MUX-ed to
the "wr" pulse of Tx FIFO.
10.2.2.2 Writing onto Rx FIFO
For writing into the Rx FIFO, the implementation is similar as above. But Rx FIFO is written in link clock domain. Hence all the
signals are synchronised from host clock domain to link clock domain.
10.2.2.3 Reading from Rx FIFO
For reading from the Rx FIFO, a PCI read cycle has to be started in the debug mode. It will generate a signal called
"FIFORdAcc_c" and assert the correct "grantType" on the "targetAddr" line, to which "noBurst" and "targetReady" will be
generated, qualifying the dataOut on the PCI Data bus from the Rx FIFO. "noBurst" is considered as "rdIncr" in the debug
mode.
10.2.2.4 Reading from Tx FIFO
For reading from Tx FIFO, the scheme is similar as above. But Tx FIFO is read in link clock domain. Hence all signals are
synchronised from host clock domain to link clock domain and vice versa.
10.2.3 Direct Read of Internal Signals
10.2.3.1 Design
The signals are clubbed into group of 32 bits and are memory mapped to Base Address 6. The access is quadlet aligned.
Hence PCI Address bus bit [1:0] will always be 2'b00. Bit[6:2] is used to map the "group of signals" to the address space.
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