82C881 Datasheet, PDF (42/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
• Each DPRAM is of 256 quadlets, as obtained from the Vendor.
• In Tx FIFO, each sub-FIFO Size is 64 quadlets.
• In Rx FIFO, Combined FIFO is of 128 quadlets. This is because it contains packets for multiple packet types. Other two
sub-FIFO’s have 64 quadlets each.
• In Tx FIFO, WriteWatermark Value is chosen as 16 quadlets as PCI can support burst up to a maximum of 16 quadlets.
• In Tx FIFO, for IT FIFO, readWatermark value is eight quadlets.
• For other sub-FIFOs in Tx FIFO, readWatermark value is 32 quadlets. This is kept high to avoid frequent hitting of
underrun as the Link operates at a higher frequency than the DMA controllers.
• In Rx FIFO, readWatermark value is 16 quadlets for each sub-FIFO. This is also to support burst on the PCI bus, so that
the FIFO does not become empty while the DMA controller is continuing a burst transfer onto the PCI bus.
In the above explanation, all values are in quadlet, unless otherwise mentioned.
10.2 Debug Features
10.2.1 Reading/Writing Tx FIFO and Rx FIFO Bypassing DMA / Link Logic
10.2.1.1 Design
The FIFOs are memory mapped to Base Address 5. The access is quadlet aligned. So PCI Address bus bit [1:0] will always be
2'b00. bit[5:2] is used to decode the FIFO accessed. Of which bit[4:2] is directly mapped with BUS_GNT ( as defined in
commonDefine.h ) for all the FIFOs, both for reading and writing.
PCI Data bus is 32 bit and FIFO Data is 33 bits ( 32 bit Data + 1 bit Tag). bit[5] of PCI address bus is used to write the value of
tag bit. If bit[5] is 1, then tag bit corresponding to that data will be 1 and vice versa.
For reading, tag bits are to be read from the FIFOs. So along with Data, tag bit is to be read. Here the 32 bit data is read out
as the pciDataOut in one read cycle. The corr. tag bit is simultaneously written in the bit[6] of miscReg in ohciRegTop. So in
the first read cycle, read access is done to the FIFO Read and in the next read cycle it is to be done to the miscReg to get the
tag bit.
Arbitration Request signal to Link Tx ( for Tx FIFO ) or RxDMA ( for Rx FIFO ) is not asserted when the chip is in debug mode.
During debug mode, read / write can only be done through PCI Cycles.
10.2.1.2 Data Format
For all the FIFOs, writing and reading of Tag bit is allowed. But to make a sensible data to be written in the FIFO, so that it can
be read as a valid packet in normal mode, the packet format per DMA / Link is to be written.
The following is the format in which the Rx FIFO receives data (32 bit) from link Rx.
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