82C881 Datasheet, PDF (18/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
4.1.4 Arbiter
Since there are seven DMA controllers, the 82C881 prioritizes the DMA controllers. To enable this functionality, the bus
request signals from all the DMA contexts are fed into the arbiter, which in turn, based on the priorities specified in 1394 OHCI
specification, decides on which DMA controller should get the grant.
4.1.5 Register Block
The Register block includes PCI bus management control and status registers (PCICFG), OHCI Registers as specified in 1394
OHCI specification, and FIFO Configuration registers. The OHCI Registers include control registers for both DMA and the Link,
and individual DMA context registers.
All registers (OHCI, PCICFG, and FIFO Configuration) are implemented in the PCICLK domain except for the Isochronous
Cycle Timer Register, which is implemented in the PHYSCLK clock domain.
Configuration of the various register blocks is described below.
4.1.5.1 OHCI DMA and Link Registers
The OHCI registers provide the standard 1394-OHCI functionality as noted in the 1394a specification.
These registers should be programmed in the sequence specified in the specification. Programming the registers in a random
order will lead to unspecified behavior.
4.1.5.2 FIFO Configuration Registers
The FIFO Configuration registers allow sizing and control of the FIFOs and provide the ability to selectively disable features of
the 1394a Link.
Programming of these registers is described elsewhere in this document and is detailed in Appendix B.
4.1.5.3 PCI Interface Registers
The logic implements the required PCI register interface for 1394 OHCI Link controllers.
PCI configuration registers are configured per PCI Local Bus Specification Revision 2.1.
4.1.6 FIFO Block
Primarily the FIFO block is used as a temporary storage place of data between DMA block on one side and the Link block on
the other. This is required as data transfer rates on the host bus interface and Link sides are different. Therefore data available
on one side, intended for transfer to the other side, is temporarily stored in the FIFO.
The DMA and Link blocks operate at two different frequencies. Therefore the FIFO block also acts as a synchronizer,
synchronizing signals from one frequency domain to other.
4.1.6.1 Tx FIFO Block
The Tx FIFO is used to store data for transmission from the transmit DMA block to the Link block, and is logically divided into
sub-FIFOs in the following order.
• Isochronous Transmit (IT)
• Asynchronous Transmit Response (AT Resp)
• Asynchronous Transmit Request (AT Req)
• Physical Response (Phy Resp)
The sub-FIFOs are configurable. Software can modify their size, Read Watermark value and Write Watermark value.
Each sub-FIFO has separate controller logic. Handshaking signals are exchanged between the corresponding Transmit-DMA-
to-Tx FIFO and Tx FIFO-to-Link before the actual transaction starts.
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