82C881 Datasheet, PDF (28/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
7
6
5
4
3
2
1
0
PCICFG 07h
Status Register - Byte 1
Detected
parity error:
This bit is set to
1 whenever the
core detects a
parity error,
even if PCICFG
04h[6] is
disabled.
Write 1 to clear.
SERR#
status:
This bit is set to
1 whenever the
core detects a
PCI address
parity error.
Write 1 to clear.
Received
master abort
status:
Set to 1 when
the core, acting
as a PCI
master, aborts
a PCI bus
memory cycle.
Write 1 to clear.
Received
target abort
status:
This bit is set to
1 when a core
generated PCI
cycle (core is
the PCI master)
is aborted by a
PCI target.
Write 1 to clear.
Signaled target
abort status:
This bit is set to
1 when the core
signals target
abort.
Write 1 to clear.
DEVSEL timing (RO):
Indicates DEVSEL# timing when
performing a positive decode.
Since DEVSEL# is asserted to
meet the medium timing, these
bits are encoded as 01.
Default = 02h
Data parity
reported:
Set to 1 if
PCICFG 04h[6]
is set and the
core detects
PERR#
asserted while
acting as PCI
master
(whether
PERR# was
driven by core
or not.)
PCICFG 08h
Revision Identification Register (RO)
Default = 00h
PCICFG 09h
PCICFG 0Ah
PCICFG 0Bh
Class Code Register (RO)
PCI-1394 OHCI Bridge
Default = 10h
Default = 00h
Default = 0Ch
PCICFG 0Ch
Cache Line Size Register
Default = 00h
PCICFG 0Dh
Master Latency Timer Register
Default = 00h
PCICFG 0Eh
Header Type Register (RO)
Default = 00h
PCICFG 0Fh
Reserved
Default = 00h
PCICFG 10h-13h
OHCI Register Set Memory Base Address
Default = 00h
This register maps the OHCI Register Set into system memory space. Bits [10:1] are always 0, requesting a 2048-byte range.
PCICFG 14h-17h
FIFO Configuration Register Set Memory Base Address
Default = 00h
This register maps the FIFO Configuration Register Set into system memory space. Bits [4:1] are always 0, requesting a 32-byte range.
Memory base address registers identify the base address of a contiguous memory space in main memory. Software will write all 1s to
this register, then read back the value to determine how big of a memory space is requested. After allocating the requested memory,
software will write the upper bytes with the base address.
Bits [31:0] correspond to: 10h = [7:0], 11h = [15:8], 12h = [23:16], 13h = [31:24].
- Bit [0] – Indicates that the operational registers are mapped into memory space. Always = 0.
- Bits [2:1] – Indicates that the base register is 32 bits wide and can be placed anywhere in 32-bit memory space. Always = 0.
- Bit [3] – Indicates no support for prefetchable memory. Always = 0.
- Bits [31:4] – Software writes the value of the memory base address to these bits.
PCICFG 18h-1Bh
OHCI Register Set I/O Base Address
Default = 00h
This register maps the OHCI Register Set into system I/O space. Bits [10:1] are always 0.
PCICFG 1Ch-1Fh
FIFO Configuration Register Set I/O Base Address
Default = 00h
This register maps the FIFO Configuration Register Set into system I/O space. Bits [4:1] are always 0, requesting a 2048-byte range.
I/O base address registers identify the base address of a contiguous range in system I/O space. Software will write all 1s to
this register, then read back the value to determine how big of an I/O range is requested. After allocating the requested space,
software will write the upper bytes with the base address.
Bits [31:0] correspond to: 10h = [7:0], 11h = [15:8], 12h = [23:16], 13h = [31:24].
- Bit [0] – Indicates that the operational registers are mapped into I/O space. Always = 1.
- Bit [1] – Always = 0.
- Bits [15:2] – Software writes the I/O base address to these bits.
- Bits [31:16] – Always = 0.
PCICFG 20h-23h
Reserved
Default = 00h
PCICFG 24h-27h
Debug Register Memory Base Address
Refer to Appendix B for details
Default = 00h
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Page 24
912-2000-031
Revision: 1.0