82C881 Datasheet, PDF (26/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
Table 2. Miscellaneous Register
7
6
5
4
3
2
1
0
OFST 1Ch
Miscellaneous Register
Default = 00h
Bits in this register are used for effecting FIFO configuration and selective enabling of P1394a features (Note 1).
Byte 0
CLKRUN#
0=Enable
1=Disable
If CLKRUN# is
asserted,
PCICLK is not
allowed to be
stopped for
power saving
mode.
FIFOTag Bit
(RO)
When in
Debug Mode,
tag bit readout
from the
Transmit
/Receive FIFO
is written to
this bit.
Debug Mode
0=Disable
1=Enable
When Debug
Mode is
enabled, the
Receive and
Transmit
FIFOs can be
read/written.
Detect
Interface
Reset in case
of 1394a
PHY
0=Enable
(if 1394a
features are
enabled)
1=Disable
Drive Idle
Before Xmit
on Link-PHY
interface
0=Enable
(if 1394a
features are
enabled)
1=Disable
Acceleration
Control
0=Enable
(if 1394a
features are
enabled)
1=Disable
Multi-Speed
Concatena-
tion
0=Enable
(if 1394a
features are
enabled)
1=Disable
FIFO
Config
Enable
(Note 2)
0=Disable
1=Enable
Note 1: All bits in this register default to 1 at Hard Reset and Soft Reset; they are not affected by bus reset.
Note 2: Software must set this bit to 1 to load register changes to the FIFO Configuration registers. The 82C881 will clear this bit after the
operation is complete.
OFST 1Dh
Byte 1
Default = 00h
Reserved
OFST 1Eh
Byte 2
Default = 00h
Reserved
OFST 1Fh
Byte 3
Default = 00h
Reserved
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912-2000-031
Revision: 1.0