82C881 Datasheet, PDF (41/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
®
82C881
10.0 APPENDIX B
10.1 FIFO Programming
FIFO Configuration Registers should be programmed in the following sequence.
• Before setting bit 0 of miscReg, check if its value is equal to zero.
• Write the New Configuration value into the individual Configuration registers.
• Set the bit 0 of miscReg (refer sec 2.4.2)
• As long as the Configuration process is going on, that bit will be one. If that bit becomes 0, it means that
Configuration process has ended. (writing into FIFO and reading from FIFO can be done only if the
configuration process has ended.)
10.1.1 Programming Notes
Points to be noted while configuring the FIFO Configuration registers:
• By setting FIFOConfigRst (bit 0 of miscReg), FIFO configuration is changed for all the FIFOs according to the FIFO
Configuration Register values present. Therefore, unwanted data should not be present in any of the FIFO Configuration
Register when the FIFOConfigRst bit gets set. If, for any FIFO, old configuration is to be retained while configuring
another FIFO, the old configuration data should be present in that FIFO Configuration Register.
• For each field of Configuration (size, readWatermark, and writeWatermark) 10 bits are allotted. But currently we are using
eight bits (The two extra bits are provided so that if the RAM size is increased then a maximum DPRAM of 1K can be
supported with the current set-up). So for Configuration, upper 8 bits should be used and lower two bits should be made
zero0.
• e.g. If a FIFO size of 64 quadlet has to be programmed, the following bit pattern has to be programmed in bits 29 to 20.
Bit 21 and 20 are not required for current implementation of 8-bit size of each field. Hence they are kept as 0.
Bit Position
29
28
27
26
25
24
23
22
21
20
Value
0
1
0
0
0
0
0
0
0
0
• All unused bits should be set to zero for the Configuration Register.
• For configuring mSpdConcatEn_n (bit 1 of miscReg), accControlEn_n (bit 2 of miscReg) drvIdlB4txEn_n (bit 3 of
miscReg) software should write into the corresponding bit. The miscReg is written as a 32-bit data bus. Thus care should
be taken not to write any unwanted data in the fields, which are of no current writing interest.
10.1.2 Important User Defined Values
Other important values to be programmed:
• The OHCI and FIFO Configuration register sets consist of 32-bit registers. This bus width is defined as:
CONFIG_BUS_WIDTH
• The size of each RAM module is 256 quadlets. Hence the address bus width is eight. It should be changed if the DPRAM
size changes.
• For Rx FIFO, it is RXFIFO_ADDRBUS_WIDTH.
• For Tx FIFO, it is TXFIFO_ADDRBUS_WIDTH
10.1.3 Current Default Configuration Values
Current Default Configuration Values and the reason for choosing them:
912-2000-031
Revision: 1.0
Page 37