82C881 Datasheet, PDF (17/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
4.1.1.1 PCI-DMA Block
The PCI-DMA block interfaces the DMA Control block to the PCI Interface block. This arrangement enables the functioning of
the DMA blocks to be independent of the Host bus that it is interfaced to. A DMA transaction is a transfer of four or fewer bytes
of data.
The PCI-DMA block translates transactions on the DMA interface to transactions on the PCI interface, aligns data to be written
out on the PCI bus, merges data fetched, and restarts transactions in case of a disconnect. It also reports errors occurring on
the PCI bus to the DMA Control block.
4.1.2 DMA Control Block
The DMA control block supports seven types of DMA. All of the seven DMA controllers can be broadly classified as TxDMA
and RxDMA.
4.1.2.1 TxDMA
The TxDMA block is made up of four sub-blocks.
• Isochronous Transmit (IT)
• Asynchronous Transmit Response (AT Resp)
• Asynchronous Transmit Request (AT Req)
• Physical Response (Phy Resp)
Each of these blocks controls the transfer of packets from the host bus to the respective Tx FIFO. Host side software sets up
the DMA “contexts,” which are essentially programmed environments used by the respective DMA sub blocks for processing
and managing movement of data. Each context consists of a programmed environment and a set of registers. The
programmed environment directs the DMA controller in the assembly of packets for transmission.
4.1.2.2 RxDMA
The RxDMA block is made up of three sub-blocks.
• Combined (Comb), consisting of:
• Isochronous Receive (IR)
• Self ID
• Asynchronous Receive Response (AR Resp)
• Asynchronous Receive (AR Req)
• Physical Receive Request (Phy Req)
This block picks out packets from the Rx FIFO, and puts them into the host memory. Host side software sets up contexts to
enable logical storage of the received packets. The registers pertaining to these contexts are programmed to achieve this. On
receiving a packet, the Rx FIFO gives an indication to the respective DMA context and the DMA context starts processing the
packet.
4.1.3 Serial EEPROM Interface
The Serial EEPROM interface is a two-wire industry-standard interface to the Serial EEPROM. This interface is capable of
performing reads as well as writes to the Serial EEPROM. Information like GUID, Device ID, Vendor ID, Class Code, Revision
ID, Subsystem ID, and Subsystem Vendor ID can be stored in the Serial PROM. These are then loaded from the Serial
EEPROM to the corresponding PCICFG registers at each power-on reset.
912-2000-031
Revision: 1.0
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