82C881 Datasheet, PDF (12/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
Signal Name
Pin
No.
Pin Signal Description
Type
IRDY#
TRDY#
44
I/O Initiator Ready: IRDY#, along with TRDY#, indicates whether the 82C881 is able
(s/t/s) to complete the current data phase of the cycle. IRDY# and TRDY# are both
asserted when a data phase is completed.
During a write, the 82C881 asserts IRDY# to indicate that it has valid data on
AD[31:0]. During a read, the 82C881 asserts IRDY# to indicate that it is prepared
to accept data.
IRDY# is an input when the 82C881 is a target and an output when it is the
initiator.
IRDY# is tristated from the leading edge of RESET# and remains tristated until
driven as either a master or a slave by the 82C881.
45
I/O Target Ready: TRDY#, along with IRDY#, indicates whether the 82C881 is able
(s/t/s) to complete the current data phase of the cycle. TRDY# and IRDY# are both
asserted when a data phase is completed.
When the 82C881 is acting as the target during read and write cycles, it performs
in the following manner:
1. During a read, the 82C881 asserts TRDY# to indicate that it has placed valid
data on AD[31:0].
2. During a write, the 82C881 asserts TRDY# to indicate that is prepared to
accept data.
STOP#
DEVSEL#
TRDY# is an input when the 82C881 is the initiator and an output when it is the
target.
TRDY# is tristated from the leading edge of RESET# and remains so until driven
as either a master or a slave by the 82C881.
48
I/O Stop: STOP# is an output when the 82C881 is the target and an input when it is
(s/t/s) the initiator. As the target, the 82C881 asserts STOP# to request that the master
stop the current cycle. As the master, the assertion of STOP# by a target forces
the 82C881 to stop the current cycle.
STOP# is tristated from the leading edge of RESET# and remains so until driven
by the 82C881 acting as a slave.
47
I/O Device Select: The 82C881 claims a PCI cycle via positive decoding by
(s/t/s) asserting DEVSEL#. As an output, the 82C881 drives DEVSEL# for two different
reasons:
1. If the 82C881 samples IDSEL active in configuration cycles, DEVSEL# is
asserted.
2. When the 82C881 decodes an internal address or when it subtractively
decodes a cycle, DEVSEL# is asserted
When DEVSEL# is an input, it indicates the target's response to an 82C881
master-initiated cycle.
DEVSEL# is tristated from the leading edge of RESET# and remains so until
driven by the 82C881 acting as a slave.
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912-2000-031
Revision: 1.0