82C881 Datasheet, PDF (19/46 Pages) List of Unclassifed Manufacturers – FireLink 1394 OHCI Link Controller

FireLink 1394 OHCI
82C881
4.1.6.2 Rx FIFO Block
The Rx FIFO aids in transmitting data from the Link to the Rx DMA block. The Rx FIFO has been logically sub divided into
sub-FIFOs in the following order:
• Combined (Comb)
• Isochronous Receive (IR)
• Self ID
• Asynchronous Receive Response (AR Resp)
• Asynchronous Receive (AR Req)
• Physical Receive Request (Phy Req)
Each sub-FIFO has separate controller logic. Handshaking signals are exchanged between the corresponding Receive-DMA-
to-Rx FIFO and Rx FIFO-to-Link before the actual transaction starts.
4.1.7 Link Block
The Link block formats the final packets from OHCI to 1394 for transmission, and also checks the received packets from the
PHY for errors and translates them back to OHCI format. While transmitting, the Link block reads the packets from different Tx
FIFOs, reformats and appends CRC information, and then gives the packets to the PHY. While receiving, after checking the
CRC information and format for errors, the Link block writes the received packets to the Rx FIFO.
The Link logic has two main blocks.
• Receive block
• Transmit block.
4.1.7.1 Receive Block
The Receive block deals with the packets in 1394 format, coming from the PHY to the 82C881. It takes data from the serial
data lines, converts it into parallel 32-bit data, performs required checks on the data, converts the data to OHCI format and
puts it into the appropriate FIFO.
The Receive Block checks the following.
• The tcode, to determine the packet type.
• The destination ID, if the packet is asynchronous. The Receive block will receive the packet only if the destination ID
matches with ID of this node.
• The request filter register to determine if this node can accept the request, if the packet is a request packet.
• The physical request filter bit to determine if this node should accept the physical request, if the packet offset address
lies within the physical range.
• The retry code, to ensure that the packet is acceptable per the dual phase retry protocol.
• The header and data CRC.
• The data length of the packet, if the packet is a block request packet. If it is greater than the maximum accepted
value, the packet is rejected.
The Receive block also generates the ack code to be sent in response to a packet and the event code in response to the
packet sent.
4.1.7.2 Transmit Block
The Transmit block deals with the packets intended for transfer from the 82C881 to the PHY. The Transmit block receives data
quadlets in OHCI format, converts them to 1394 packet format, adds CRC information and converts the packets for
transferring to the PHY.
912-2000-031
Revision: 1.0
®
Page 15