SD1010D Datasheet, PDF (32/40 Pages) List of Unclassifed Manufacturers – Digital Interface VGA TFT LCD Display Controller

Auto_iq_valid
Divisor_valid
Non_full_screen
Href_reg
Vref_reg
Text Control
1
R 4EH[2] Indicates when image quality is ready for cpu to read in
auto calibrate mode. Read only
1
R 4EH[1] Indicates when auto clock frequency calibration is done
and frequency value is ready for cpu to read. Read only
1
R 4EH[0] Indicates when input data is non full screen. Read only
8
R
4FH This reg reports the period of hsync by counting the
number of free clock cycle in one single hsync period.
16
R 50H-51H This reg reports the period of vsync by counting the
number of free clock cycle in one single vsync period.
8
RW 52H[7:0] Text-Enhancement Control
Bit[0]: text enhancement enable
0: disable
1: enable
Bit[1]: Reserved
Bit[6:2]: text-enhanced level
Level 0 – 14. Level “0” is the same as original source,
and “14” is the highest enhancement level.
Bit[7]: Reserved
Default is 00H
Sharpness Control
8
RW 53H[7:0] Sharpness-Enhancement Control
Bit[0]: sharpness enhancement enable
0: disable
1: enable
Bit[1]: Reserved
Bit[6:2]: sharpness-enhanced level
Level 1 – 19. Level “5” is the same as the original
source. From “4” to “1” intend to soften the picture,
and “1” is the softest level. From level “6” to “19” will
sharpen the picture gradually. Level “19” is the
sharpest output.
Bit[7]: Reserved
Control_E
Default is 14H
8
RW 54H[7:0] Control Register E
Bit[3:0]: text enhancement threshold.
Bit[4]: reserved
Bit[6:5]: Frame Modulation Mode
0: compatible with SD1010
1-3: new schemes
Bit[7]: reserved
Pixel_h
Pixel_v
Default is 05H
11 RW 55H[10:8] The x location for reading “Pixel_out” register
56H[7:0]
11 RW 57H[10:8] The y location for reading “Pixel_out” register
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