SD1010D Datasheet, PDF (24/40 Pages) List of Unclassifed Manufacturers – Digital Interface VGA TFT LCD Display Controller

Reserved
8
258H
Calibration mode
2
259H [1:0] Selects different operation modes of internal phase
calibration. The selection criterion is as follows:
(This entry is not used)
0: when input video signal has large overshot,
it results in longest calibration time
1: when input video signal has median overshot,
it results in long calibration time
2: when input video signal has normal overshot,
it results in normal calibration time
(recommended)
3: when input video signal has no overshot,
it results in shortest calibration time
PWM unit delay
16 25AH-25BH The unit delay used in the external PWM delay circuitry.
If the free-running clock is 1MHz, and the intended unit
delay is 0.2 ns (= 5,000MHz), then a value of
5,000MHz/1MHz = 5,000 is used here.
(This entry is not used)
Maximum link off time
22 25CH-25EH Maximum time when input HSYNC is off before the
LINK_DWN pin turns ON (unit: clock period of the free
running clock). If the free-running clock is 1MHz, and the
intended maximum time is 1 second, then a value of
1,000,000 µs/ 1 µs = 1,000,000 is used here.
Maximum refresh rate
16 25FH-260H Maximum refresh rate supported by the LCD panel.
If the intended maximum refresh rate is 75Hz, and the
free-running clock is 1MHz, then a value of
1000000/75=133,333 is used here
Maximum input
frequency
8
261H Maximum source clock rate supported by the SD1010
(unit: frequency of free-running clock).
If the intended maximum clock rate is 60MHz, and the
free-running clock is 1MHz, then a value of 60 is used
here.
If the input signal has a higher frequency than this value,
the VCLK0_X status bit will turn ON.
Minimum pixels per line 11
for LCD
262H-263H Minimum number of pixels per line for LCD panel
Switching options
1
264H[4] Enable for switching to standalone hsync and vsync
during no input conditions: Default is 1
1: cpu controls the switching
0: SD1010D controls the switching.
LCD polarity
4 264H[3:0] _{Controls the polarity of output VSYNC,}
HSYNC, clock and display enable:Bit0: 0:
clock active high, 1: clock active low
Bit1: 0: HSYNC active low, 1: HSYNC active high
Bit2: 0: VSYNC active low, 1: VSYNC active high
Bit4: 0: de active high, 1: de active low
Output enable for output
1
in 51-54, 56-59, 61-64,
6-69, 71-74, 76-79, 81-
4, 86-89, 91-97, 99,
01-104, 106-109
265H[3] Enable for programmable output pad:
1: output is enabled
0: output is tri-state
Driving capability
3
ontrol for output pin
1-54, 56-59, 61-64, 66-
9, 71-74, 76-79, 81-84,
6-89, 91-97, 99, 101-
04, 106-109
265H[2:0]
0: 2mA
1: 6mA
2: 6mA
3: 10mA
4: 4mA
5: 8mA
525 Race Street, Suite 250, San Jose, CA 95126, USA.
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