SD1010D Datasheet, PDF (10/40 Pages) List of Unclassifed Manufacturers – Digital Interface VGA TFT LCD Display Controller

G_OUT4_E
G_OUT5_E
G_OUT6_E
G_OUT7_E
G_OUT0_O
G_OUT1_O
G_OUT2_O
G_OUT3_O
G_OUT4_O
G_OUT5_O
G_OUT6_O
G_OUT7_O
B_OUT0_E
B_OUT1_E
B_OUT2_E
B_OUT3_E
B_OUT4_E
B_OUT5_E
B_OUT6_E
B_OUT7_E
B_OUT0_O
B_OUT1_O
B_OUT2_O
B_OUT3_O
B_OUT4_O
B_OUT5_O
B_OUT6_O
B_OUT7_O
HSYNC_O
VSYNC_O
DCLK_OUT
DE_OUT
FCLK0
VCLK0
FCLK1
VCLK1
ROM_SCL
ROM_SDA
CPU_SCL
CPU_SDA
PWM_CTL
CLK_1M
CLK_1M_O
51
O Output Color Green Even Pixel (left pixel)
53
O Output Color Green Even Pixel (left pixel)
54
O Output Color Green Even Pixel (left pixel)
55
O Output Color Green Even Pixel (left pixel)
58
O Output Color Green Odd Pixel (right pixel)
59
O Output Color Green Odd Pixel (right pixel)
60
O Output Color Green Odd Pixel (right pixel)
61
O Output Color Green Odd Pixel (right pixel)
63
O Output Color Green Odd Pixel (right pixel)
64
O Output Color Green Odd Pixel (right pixel)
65
O Output Color Green Odd Pixel (right pixel)
66
O Output Color Green Odd Pixel (right pixel)
69
O Output Color Blue Even Pixel (left pixel)
70
O Output Color Blue Even Pixel (left pixel)
71
O Output Color Blue Even Pixel (left pixel)
72
O Output Color Blue Even Pixel (left pixel)
73
O Output Color Blue Even Pixel (left pixel)
74
O Output Color Blue Even Pixel (left pixel)
75
O Output Color Blue Even Pixel (left pixel)
78
O Output Color Blue Even Pixel (left pixel)
80
O Output Color Blue Odd Pixel (right pixel)
81
O Output Color Blue Odd Pixel (right pixel)
82
O Output Color Blue Odd Pixel (right pixel)
83
O Output Color Blue Odd Pixel (right pixel)
85
O Output Color Blue Odd Pixel (right pixel)
86
O Output Color Blue Odd Pixel (right pixel)
87
O Output Color Blue Odd Pixel (right pixel)
88
O Output Color Blue Odd Pixel (right pixel)
21
O Output HSYNC (the polarity is programmable
through CPU, default is active low)
22
O Output VSYNC (the polarity is programmable
through CPU, default is active low)
23
O Output Clock to Control Panel (the polarity is
programmable through CPU)
24
O Output Display Enable for Panel (the polarity is
programmable through CPU, default is active HIGH)
17
O Input PLL Feedback Clock (not used)
18
I Input Clock 0 (not used)
19
O Output PLL Feedback Clock
20
I Output PLL Output Clock
1
O SCL in I²C for EEPROM interface
2
I/O SDA in I²C for EEPROM interface
4
I SCL in I²C for CPU interface
5
I/O SDA in I²C for CPU interface
6
O PWM control signal (not used)
7
I Free Running Clock (default: 1MHz)
9
O Feedback of free Running Clock
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