SD1010D Datasheet, PDF (13/40 Pages) List of Unclassifed Manufacturers – Digital Interface VGA TFT LCD Display Controller

ii)
Input mode detection
The SD1010D can automatically detect the mode of the input signal without any user
adjustment or driver running on the PC host or external CPU. This block automatically detects
polarity of input synchronization and the sizes of back porch, valid data window and the
synchronization pulse width in both vertical and horizontal directions. The size information is
then used not only to decide the input resolution, to lock the PLL output clock with HSYNC,
but also to automatically scale the image to full screen and to synchronize the output signal with
the input signal.
The detection logic is always active to automatically detect any changes to the input mode.
Users can manually change the input mode information at run time through the CPU interface.
Detailed operation of the CPU interface is described in Section 3.6. “CPU Interface”.
Mode detection can be independently turned ON or OFF by the external CPU. This feature
allows system customers to have better control of the mode-detection process. When the
detection is turned OFF, the external CPU can change the input mode.
iii)
Free Running Clock
As described in previous section, a free-running clock is needed for the SD1010D. This clock is
used for many of the SD1010D’s internal operations. Eeprom operation is one of them. System
manufacturers can select the frequency of the free-running clock, and the default clock
frequency is 1MHz. System manufacturers can use an oscillator to generate the free-running
clock, and feed that clock directly to the pin “CLK_1M”, or use a crystal connecting to
“CLK_1M” and “CLK_1M_O”.
Buffer memory and read/write control block
The SD1010D uses internal buffer memory to store a portion of the input image for image
scaling and output synchronization. No external memory buffer is needed for the SD1010D.
The write control logic ensures the input data are stored into the right area of the buffer
memory, and the read control logic is responsible to fetch the data from the buffer memory from
the correct area and at the correct timing sequence. With the precise timing control of the write
and read logic, the output image is appropriately scaled to the full screen, and the output signal
is perfectly synchronized with the input signals.
Image scaling, interpolation and dithering block
The SD1010D supports both automatic image scaling and interpolation.
iv)
Image scaling
The SD1010D supports several different input modes, and the input image may have different
sizes. It is essential to support automatic image scaling so that the input image is always
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