SD1010D Datasheet, PDF (26/40 Pages) List of Unclassifed Manufacturers – Digital Interface VGA TFT LCD Display Controller

Part 16: Gamma Correction Lookup Table
Symbol
Mapped value
Check sum
Mapped value
Check sum
Mapped value
Check sum
Width
(bits)
8
8
8
8
8
8
Address
Description
2C0H-3BFH This is the lookup table for the gamma correction function
If 200H[7] = 0, the mapped value is used for all RGB
If 200H[7] = 1, the mapped value is used only for R
3C0H Sum of above 256 bytes (keep only lower 8 bit)
420H-51FH This is the lookup table for the gamma correction function
for green. This is needed only if 200H[7]=1
520H Sum of above 256 bytes (keep only lower 8 bits)
5A0H-69FH This is the lookup table for the gamma correction function
for blue. This is needed only if 200H[7] = 1
6A0H Sum of above 256 bytes (keep only lower 8 bits)
CPU interface
The SD1010D supports a 2-wire serial interface to an external CPU. The interface allows the external CPU to
access and modify control registers inside the SD1010D. The 2-wire serial interface is similar to the EEPROM
interface, and the CPU is the host that drives the SCL all the time as the clock and for “start” and “stop” bits.
The SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. This interface supports
random and sequential write operations for the CPU to modify one or multiple control registers, and random
and sequential read operations for the CPU to read all or part of the control registers.
The default device ID for the SD1010D is fixed “1111111”. The device ID can be programmed through
EEPROM entry 200H bit 0 through bit 6. This avoids any conflict with other 2-wire serial devices on the same
bus.
The following table briefly describes the SD1010D control registers. The external CPU can read these registers
to know the state of the SD1010D as well as the result of input mode detection and phase calibration. The
external CPU can modify these control registers to disable several SD1010D features and force the SD1010D
into a particular state. When the CPU modifies the control registers, the new data will be first stored in a set of
shadow registers, and then copied into the actual control registers when the “CPU Control Enable” bit is set.
When the “CPU Control Enable” bit is set, the external CPU will retain control and the SD1010D will not
perform the auto mode detection and auto calibration.
The external CPU is able to adjust the size of the output image and move the output image up and down by
simply changing the porch size and pixel and line numbers of the input signal. These adjustments can be tied to
the external user control button on the monitor.
A set of four control registers are used to generate output signal when there is no input signal available to the
SD1010D or the input signal is beyond the acceptable ranges. This operation mode is called standalone mode,
which is very important for the end users when they accidentally select an input mode beyond the acceptable
range of the SD1010D or when the input cable connection becomes loose for any reason. System manufacturers
can display appropriate OSD warning messages on the LCD panel to notify the users about the problem.
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