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M13S128324A Datasheet, PDF (8/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM
◁
ESMT
M13S128324A
AC Timing Parameter & Specifications-continued
Parameter
Half Clock Period
DQ-DQS output hold time
ACTIVE to PRECHARGE
command
Symbol
tHP
tQH
tRAS
-3.6
Min
tCLmin
or
tCHmin
tHP-0.
4
11
Max
-
-
120K
ns
-4(CL3)
Min
tCLmin
or
tCHmin
tHP-0.
45
10
Max
-
-
120K
ns
-4
Min
tCLmin
or
tCHmin
tHP-0.
45
10
Max
-
-
120K
ns
-5
Min
tCLmin
or
tCHmin
tHP-0.
45
8
Max
-
-
120K
ns
-6
Min
tCLmin
or
tCHmin
tHP-0.
5
7
Max
-
-
120K
ns
Row Cycle Time
tRC
16
-
15
-
15
-
12
-
10
-
AUTO REFRESH Row Cycle
Time
tRFC
18
-
17
-
17
-
14
-
12
-
ACTIVE to READ,WRITE
delay
tRCD
5
-
5
-
5
-
4
-
3
-
PRECHARGE command
period
tRP
4
-
4
-
4
-
4
-
3
-
ACTIVE to READ with
AUTOPRECHARGE
command
tRAP
4
-
4
-
4
-
4
-
3
-
ACTIVE bank A to ACTIVE
bank B command
tRRD
3
-
3
-
3
-
2
-
2
-
Write recovery time
Write data in to READ
command delay
tWR
15
-
15
-
15
-
15
-
15
-
tWTR
2
-
2
-
2
-
2
-
2
-
Col. Address to Col. Address
delay
tCCD
1
-
1
-
1
-
1
-
1
-
Average periodic refresh
interval
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
Write preamble
tWPRE 0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
Write postamble
tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
DQS read preamble
tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6 0.4 0.6 0.4 0.6
Clock to DQS write preamble
setup time
tWPRES
0
-
0
-
0
-
0
-
0
-
Load Mode Register /
Extended Mode register
cycle time
tMRD
2
-
2
-
2
-
2
-
2
-
Exit self refresh to READ
command
tXSRD
200
-
200
-
200
-
200
-
200
-
Exit self refresh to
non-READ command
Autoprecharge write
recovery+Precharge time
tXSNR
75
-
75
-
75
-
75
-
75
-
(tWR/tC
(tWR/tC
(tWR/tC
(tWR/tC
(tWR/tC
tDAL
K)
+(tRP/t
-
K)
+(tRP/t
-
K)
+(tRP/t
-
K) +
(tRP/tC
-
K)
+(tRP/t
-
CK)
CK)
CK)
K)
CK)
Unit
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
tCK
tCK
us
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
tCK
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
8/49
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