M13S128324A Datasheet, PDF (18/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous
burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the
first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is
satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4, CAS Latency = 3>
0
1
CLK
CLK
2
3
COMMAND READ A
READ B
NOP
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
CAS Latency=3
DQS
DQ's
t_CCD
Dou t A0 Dou t A1 Dout B0 Dout B1 Dout B2 Dout B3
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O
bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the
beginning the write operation, Burt stop command must be applied at least RU(CL) clocks ï¼»RU means round up to the nearest
integerï¼½ before the Write command.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
CLK
CLK
COMMAND READ
Burst Stop
NOP
NOP
W RITE
NOP
6
NOP
7
NOP
8
NOP
CAS Latency=3
DQS
DQ's
Dout 0 Dout 1
Din 0 Din 1 Din 2 Din 3
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
18/49