M13S128324A Datasheet, PDF (26/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
Write with Auto Precharge
If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping
t_WR(min).
<Burst Length = 4>
0
1
2
CLK
CLK
COMMAND
Bank A
ACTIVE
NOP
Write A
Auto Precharge
3
NOP
4
NOP
5
6
NOP
NOP
7
NOP
8
NOP
DQS
DQ's
Auto Refresh & Self Refresh
Dout 0 Dout 1 Dout 2 Dout 3
*Bank can be reactivated at
completion of tRP
tWR
In tern al p rech arge start
tRP
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge
of the clock(CLK). All banks must be precharged and idle for t_RP(min) before the auto refresh command is applied. No control of
the external address pins is requires once this cycle has started because of the internal address counter. When the refresh
cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate
command or subsequent auto refresh command must be greater than or equal to the t_RFC(min).
CLK
CLK
COMMAND
CKE = High
PRE
Au t o
Refresh
tRP
tRFC
CMD
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
26/49