M13S128324A Datasheet, PDF (37/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Write with Auto Precharge (@BL=8)
M13S128324A
CLK
CLK
CKE
CS
RAS
CAS
BA0,BA1
A8/AP
ADDR
(A0~An)
WE
DQS
DQ
DM
COMMAND
0
1
2
3
4
5
6
7
8
9
10
HIGH
BAa
Ca
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
BAa
Ra
Ra
tWR
tDAL
Auto precharge start
Note1
tRP
WRITE
ACTIVE
Note 1.
The row active command of the precharge bank can be issued after t_RP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
37/49