M13S128324A Datasheet, PDF (25/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2
clock later from a read with auto-precharge command when t_RAS(min) is satisfied. If not, the start point of precharge operation
will be delayed until t_RAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the
new command can not be asserted until the precharge time (t_RP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
CL K
C LK
C OM M A ND
Ba nk A
A CTI VE
CA S Lat en cy=3
DQS
DQ's
NOP
t R AP
R ea d A
Auto Pre cha rg e
NOP
4
NOP
5
6
7
NOP
NOP
NOP
D o ut 0 Do u t 1 Do u t 2 Do u t 3
8
NOP
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
25/49