M13S128324A Datasheet, PDF (33/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
M13S128324A
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
33/49