M13S128324A Datasheet, PDF (6/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
DC Specifications
M13S128324A
Parameter
Symbol
Test Condition
Version
-3.6 -4
-5
-6
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
IDD0
t_RC = t_RC (min) t_CK = t_CK (min)
Active – Precharge
235 210 175 145
Burst Length = 2 t_RC = t_RC (min),
IDD1 ^{CL= 2.5 I}OUT ^{= 0mA,}
245 220 190 180
Active-Read- Precharge
IDD2P
CKE ≤ V_IL(max), t_CK = t_CK (min),
All banks idle
40
40
40
40
Idle Standby Current
IDD2N ^{CKE ≥ VIH(min), CS ≥}
V_IH(min), t_CK = t_CK (min)
135 120 115 95
Active Power-down Standby
Current
IDD3P
All banks ACT, CKE ≤ V_IL(max),
t_CK = t_CK (min)
60
55
50
45
Active Standby Current
One bank; Active-Precharge, t_RC
IDD3N = t_RAS(max),
150 130 120 110
t_CK = t_CK (min)
Operation Current (Read)
IDD4R
Burst Length = 2, CL= 2.5 , t_CK =
t_CK (min), I_OUT = 0Ma
440
400
350
300
Operation Current (Write)
IDD4W
Burst Length = 2, CL= 2.5 , t_CK =
t_CK (min)
470
430
380
330
Auto Refresh Current
IDD5 t_RC ≥ t_RFC(min)
320 290 270 250
Self Refresh Current
IDD6 CKE ≤ 0.2V
3
3
3
3
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
Unit
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note
-
-
-
-
-
-
-
-
-
-
1
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
V_IX(AC)
Min
V_REF + 0.35
-
0.7
Max
-
V_REF - 0.35
V_DDQ+0.6
0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
Unit
V
V
V
V
Note
-
-
1
2
Note1. V_ID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of
the same.
Input / Output Capacitance
(V_DD = 2.375V~2.75V, V_DDQ =2.375V~2.75V, T_A = 25 °C , f = 1MHz)
(V_DD = 2.5V~2.7V, V_DDQ =2.5V~2.7V, T_A = 25 °C , f = 1MHz (for speed -3.6))
(V_DD = 2.6V~2.8V, V_DDQ =2.6V~2.8V, T_A = 25 °C , f = 1MHz [only for speed -4(CL3)])
Parameter
Symbol Min
Max
Unit
Input capacitance(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
C_IN1
1
4
pF
Input capacitance (CLK, CLK )
C_IN2
1
5
pF
Data & DQS input/output capacitance
Input capacitance (DM)
C_OUT
1
6.5
pF
C_IN3
1
6.5
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
6/49