M13S128324A Datasheet, PDF (1/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Revision History
Revision 0.1 (May. 13 2005)
-Original
Revision 0.2 (Aug. 08 2005)
-Delete Non-Pb-free of ordering information
-Modify typing error of Pin Arrangement
Revision 1.0 (Mar. 08 2006)
-Delete “Preliminary” at every page
-Modify tWR from 2clk to 15ns
-Modify tWTR from 1clk to 2ns
Revision 1.1 (Oct. 25 2006)
-Add -4BG spec (only for CL4)
Revision 1.2 (Nov. 16 2006)
-Add 100 pin LQFP package
Revision 1.3 (Mar. 02 2007)
-Delete BGA ball name of packing dimensions
Revision 1.4 (Mar. 12 2007)
-Add -3.6 speed grade
Revision 1.5 (Mar. 21 2007)
-Add -4(CL3) specification
Revision 1.6 (Mar. 29 2007)
- Modify A10 to A8 on P26
- Modify the figure on P37
Revision 1.7 (Apr. 17 2007)
- Modify -4(CL3) VDD; VDDQ; spec
Revision 1.8 (May. 2 2007)
- Modify PD spec
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
1/49