M13S128324A Datasheet, PDF (2/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
DDR SDRAM
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2; 2.5; 3;4
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8, full page
z Full page burst length for sequential burst type only
z Start address of the full page burst should be even
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z V_DD = 2.375V ~ 2.625V, V_DDQ = 2.375V ~ 2.625V
z V_DD = 2.5V ~ 2.7V, V_DDQ = 2.5V ~ 2.7V [for speed -3.6]
z Auto & Self refresh
z 32ms refresh period (4K cycle)
z SSTL-2 I/O interface
z 144Ball FBGA and 100 pin LQFP package
Operating Frequencies :
PRODUCT NO.
MAX FREQ
VDD
PACKAGE COMMENTS
M13S128324A -3.6BG
275MHz
2.6V 144 Ball FBGA Pb-free
M13S128324A -4BG
250MHz
2.5V 144 Ball FBGA Pb-free
M13S128324A -5BG
200MHz
2.5V 144 Ball FBGA Pb-free
M13S128324A -6BG
166MHz
2.5V 144 Ball FBGA Pb-free
M13S128324A -4LG
250MHz
2.5V
100 pin LQFP
Pb-free
M13S128324A -5LG
200MHz
2.5V
100 pin LQFP
Pb-free
M13S128324A -6LG
166MHz
2.5V
100 pin LQFP
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
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