M13S128324A Datasheet, PDF (4/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Pin Arrangement
M13S128324A
DQ29
81
VSSQ
82
DQ30
83
DQ31
84
VSS
85
VDDQ
86
N.C
87
N.C
88
N.C
89
N.C
90
N.C
91
VSSQ
92
N.C
93
DQS
94
VDDQ
95
VDD
96
DQ0
97
DQ1
98
VSSQ
99
DQ2
100
100 Pin LQFP
Forward Type
20 x 14 mm
0.65 mmpin Pitch
50
A7
49
A6
48
A5
47
A4
46
VSS
45
A9
44
N.C
43
N.C
42
N.C
41
N.C
40
N.C
39
N.C
38
N.C
37
A11
36
A10
35
VDD
34
A3
33
A2
32
A1
31
A0
Pin Description
(M13S128324A)
Pin Name
A0~A11,
BA0,BA1
Function
Address inputs
- Row address A0~A11
- Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
DQ0~DQ31 Data-in/Data-out
RAS
CAS
WE
V_SS
V_DD
DQS0~DQS3
(for FBGA)
DQS
(for LQFP)
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~DQ7.
DQS1 correspond to the data on DQ8~DQ15.
DQS2 correspond to the data on DQ16~DQ23.
DQS3 correspond to the data on DQ24~DQ31.
Bi- directional Data Strobe.
Pin Name
Function
DM0~DM3 DQ Mask enable in write cycle.
CLK, CLK
CKE
CS
V_DDQ
V_SSQ
V_REF
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL
NC
No connection
-
-
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
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