M13S128324A Datasheet, PDF (13/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is
not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended
mode register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all
bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A9 and
BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. The mode register
contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and
BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0
A9
A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0
1
RFU: Must be set “0” D.I.C RFU: Must be set “0” D.I.C DLL Extended Mode Register
A6 A1
0
0
0
1
1
0
1
1
Output Driver Impedance Control
Normal
Weak
RFU
Matched Impedance
BA1 BA0 Operating Mode
0
0
MRS Cycle
0
1
EMRS Cycle
A0 DLL Enable
0
Enable
1
Disable
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
13/49