M14D2561616A Datasheet, PDF (6/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D2561616A
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
Version
Unit
-2.5
-3
One bank;
Operating Current
(Active - Precharge)
IDD0
t_CK = t_CK (IDD), t_RC = t_RC (IDD), t_RAS = t_RAS (IDD)min;
CKE is High, CS is HIGH between valid commands;
70
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I_OUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
Operating Current
t_CK = t_CK (IDD), t_RC = t_RC (IDD),
(Active - Read -
Precharge)
IDD1 t_RAS = t_RAS (IDD)min, t_RCD = t_RCD (IDD);
85
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
65
mA
80
mA
Precharge
Power-Down
Standby Current
IDD2P
All banks idle;
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
10
10
mA
All banks idle;
Precharge Quiet
Standby Current
IDD2Q ^{tCK = tCK (IDD); CKE is HIGH, CS is HIGH;}
Other control and address bus inputs are STABLE;
15
Data bus inputs are FLOATING
All banks idle;
t_CK = t_CK (IDD); CKE is HIGH, CS is HIGH;
Idle Standby Current IDD2N _{Other control and address bus inputs are SWITCHING;}
20
Data bus inputs are SWITCHING
15
mA
20
mA
All banks open;
Fast PDN Exit
15
Active Power-down
Standby Current
IDD3P
t_CK = t_CK (IDD); CKE is LOW;
Other control and address bus inputs
MRS(12) = 0
are STABLE;
Slow PDN Exit
12
Data bus input are FLOATING
MRS(12) = 1
Active Standby
Current
All banks open;
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD3N CKE is HIGH, CS is HIGH between valid commands;
40
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I_OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Read)
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD4R _{CKE is HIGH, CS is HIGH between valid commands;}
170
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
Operation Current
(Write)
t_CK = t_CK (IDD), t_RAS = t_RAS (IDD)max, t_RP = t_RP (IDD);
IDD4W _{CKE is HIGH, CS is HIGH between valid commands;}
160
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
15
mA
12
35
mA
145
mA
140
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
6/59