M14D2561616A Datasheet, PDF (41/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D2561616A
Write Interrupted by a Write
Burst Wirte can only be interrupted by another Write with 4 bit burst boundary. Any other case of Write interrupt is not allowed.
< CL= 3; AL= 0; RL= 3; WL= 2; BL= 8 >
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP NOP
DQS,DQS
DQs
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
Note:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read
command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst
interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the MRS. They are not referenced to actual
burst. For example, minimum Write to Precharge timing is WL+BL/2+ t_WR where t_WR starts with the rising
clock after the un-interrupted burst end and not from the end of actual burst end.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
41/59