M14D2561616A Datasheet, PDF (14/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D2561616A
7. t_QHS accounts for:
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HP at the input is
transferred to the output; and
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both
of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel
variation of the output drivers.
8. t_QH = t_HP - t_QHS, where:
t_HP is the minimum of the absolute half period of the actual input clock; and t_QHS is the specification value under the max
column. {The less half-pulse width distortion present, the larger the t_QH value is; and the larger the valid data eye will be.}
Examples:
a. If the system provides t_HP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides t_QH of 975 ps minimum.
b. If the system provides t_HP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides t_QH of 1080 ps minimum.
9. RU stands for round up. WR refers to the t_WR parameter stored in the MRS.
10. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_ERR (6-10per) of the
input clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has t_ERR (6-10per)(min.) = - 272 ps and t_ERR (6-10per)(max.) =
+ 293 ps, then t_DQSCK (min.)(derated) = t_DQSCK (min.) - t_ERR (6-10per)(max.) = - 400 ps - 293 ps = - 693 ps and t_DQSCK (max.)
(derated) = t_DQSCK (max.) - t_ERR (6-10per)(min.) = 400 ps + 272 ps = + 672 ps. Similarly, t_LZ (DQ) for DDR2-667 de-rates to t_LZ
(DQ)(min.)(derated) = - 900 ps - 293 ps = - 1193 ps and t_LZ (DQ)(max.)(derated) = 450 ps + 272 ps = + 722 ps.
11. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_JIT (per) of the input
clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has t_JIT (per)(min.) = - 72 ps and t_JIT (per)(max.) = + 93 ps, then
t_RPRE (min.)(derated) = t_RPRE (min.) + t_JIT (per)(min.) = 0.9 x t_CK (avg) - 72 ps = + 2178 ps and t_RPRE (max.)(derated) = t_RPRE
(max.) + t_JIT (per)(max.) = 1.1 x t_CK (avg) + 93 ps = + 2843 ps.
12. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_JIT (duty) of the input
clock. (output de-ratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has t_JIT (duty)(min.) = - 72 ps and t_JIT (duty)(max.) = + 93 ps,
then t_RPST (min.)(derated) = t_RPST (min.) + t_JIT (duty)(min.) = 0.4 x t_CK (avg) - 72 ps = + 928 ps and t_RPST (max.)(derated) =
t_RPST (max.) + t_JIT (duty)(max.) = 0.6 x t_CK (avg) + 93 ps = + 1592 ps.
13. Refer to the Clock Jitter table.
14. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from t_AOND.
15. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from t_AOFD.
16. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual t_ERR (6-10per) of the
input clock. (output de-ratings are relative to the SDRAM input clock.)
17. When the device is operated with input clock jitter, this parameter needs to be derated by { - t_JIT (duty)(max.) - t_ERR
(6-10per)(max.) } and { - t_JIT (duty)(min.) - t_ERR (6-10per)(min.) } of the actual input clock. (output deratings are relative to the
SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has t_ERR (6-10per)(min.) = - 272 ps, t_ERR (6- 10per)(max.) = +
293 ps, t_JIT (duty)(min.) = - 106 ps and t_JIT (duty)(max.) = + 94 ps, then t_AOF(min.)(derated) = t_AOF(min.) + { - t_JIT (duty)(max.) -
t_ERR (6-10per)(max.) } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and t_AOF(max.)(derated) = t_AOF(max.) + { - t_JIT (duty)(min.) -
t_ERR (6-10per)(min.) } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps.
18. For t_AOFD of DDR2-667/800, the 1/2 clock of t_CK in the 2.5 x t_CK assumes a t_CH (avg), average input clock HIGH pulse width of
0.5 relative to t_CK (avg). t_AOF (min.) and t_AOF (max.) should each be derated by the same amount as the actual amount of t_CH
(avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case t_CH (avg) of 0.48, the t_AOF (min.) should be derated by subtracting 0.02 x t_CK
(avg) from it, whereas if an input clock has a worst case t_CH (avg) of 0.52, the t_AOF (max.) should be derated by adding 0.02 x
t_CK (avg) to it. Therefore, we have;
t_AOF (min.)(derated) = t_AC (min.) - [0.5 - Min(0.5, t_CH (avg)(min.))] x t_CK (avg)
t_AOF (max.)(derated) = t_AC (max.) + 0.6 + [Max(0.5, t_CH (avg)(max.)) - 0.5] x t_CK (avg)
or
t_AOF (min.)(derated) = Min(t_AC (min.), t_AC (min.) - [0.5 - t_CH (avg)(min.)] x t_CK (avg))
t_AOF (max.)(derated) = 0.6 + Max(t_AC (max.), t_AC (max.) + [t_CH (avg)(max.) - 0.5] x t_CK (avg)), where:
t_CH (avg)(min.) and t_CH (avg)(max.) are the minimum and maximum of t_CH (avg) actually measured at the DRAM input balls.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
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