M14D2561616A Datasheet, PDF (48/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D2561616A
Self Refresh
A Self Refresh command is defined by having CS , RAS , CAS and CKE held LOW with WE HIGH at the rising edge of the
clock (CLK). ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS(1)
command. Once the command is registered, CKE must be held LOW to keep the device in Self Refresh mode. The DLL is
automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the device has
entered Self Refresh mode, all of the external signals except CKE, are “don’t care”.
For proper Self Refresh operation all power supply pins (V_DD, V_DDQ, V_DDL and V_REF) must be at valid levels. The device initiates a
minimum of one refresh command internally within t_CKE period once it enters Self Refresh mode. The clock is internally disabled
during Self Refresh operation to save power. Self Refresh mode must be remained t_CKE (min).
The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered,
however, the clock must be restarted and stable before the device can exit Self Refresh operation. The procedure for exiting Self
Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit
is registered, a delay of t_XSRD(min) must be satisfied before a valid command can be issued to the device to allow for any internal
refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period t_XSRD for proper operation except for Self
Refresh re-entry. Upon exit from Self Refresh, the device can be put back into Self Refresh mode after waiting t_XSNR(min) and
issuing one Refresh command. NOP or deselect commands must be registered on each positive clock edge during the Self
Refresh exit interval t_XSNR. ODT should be turned off during t_XSRD. The use of Self Refresh mode introduces the possibility that an
internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the
device requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
tCK
tCH tCL
CLK
CLK
tRP
>= tXSNR
>= tXSRD
CKE
tAOFD
tIS
tIS
ODT
tIS
Command
tIS tIH
Note:
1. Device must be in the “All banks idle” state prior to entering Self Refresh mode.
2. ODT must be turned off t_AOFD before entering Self Refresh mode, and can be turned on again when t_XSRD
timing is satisfied.
3. t_XSRD is applied for a Read or a Read with Auto Precharge command.
4. t_XSNR is applied for any command except a Read or a Read with Auto Precharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
48/59