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M14D2561616A Datasheet, PDF (1/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM
ESMT
M14D2561616A
DDR II SDRAM
4M x 16 Bit x 4 Banks
DDR II SDRAM
Features
z JEDEC Standard
z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
z Internal pipelined double-data-rate architecture; two data access per clock cycle
z Bi-directional differential data strobe (DQS, /DQS); /DQS can be disabled for single-ended data strobe operation.
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 3, 4, 5, 6
z Additive Latency: 0, 1, 2, 3, 4
z Burst Type : Sequential and Interleave
z Burst Length : 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READ; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z Off-Chip-Driver (OCD) impedance adjustment
z On-Die-Termination for better signal quality
z Special function support
- 50/ 75/ 150 ohm ODT
- High Temperature Self refresh rate enable
z Auto & Self refresh
z Refresh cycle :
- 8192 cycles/64ms (7.8μs refresh interval) at 0 ℃ ≦ TC ≦ +85 ℃
- 8192 cycles/32ms (3.9μs refresh interval) at +85 ℃ < TC ≦ +95 ℃
z SSTL_18 interface
z 84-ball BGA package
Ordering Information:
PRODUCT NO.
MAX FREQ
VDD
M14D2561616A -2.5BG
M14D2561616A -3BG
400MHz
333MHz
1.8V
1.8V
Data rate
(CL-tRCD-tRP)
DDR2-800 (5-5-5)
DDR2-800 (6-6-6)
DDR2-667 (5-5-5)
PACKAGE
COMMENTS
BGA
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
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