M14D2561616A Datasheet, PDF (25/59 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks DDR II SDRAM

ESMT
M14D2561616A
Extended Mode Register Set-1 [EMRS(1)]
The EMRS(1) stores the data for enabling or disabling DLL, output driver strength, additive latency, ODT, disable
, OCD
program. The default value of the EMRS(1) is not defined, therefore EMRS(1) must be written after power up for proper operation.
The EMRS(1) is written by asserting LOW on CS , RAS , CAS , WE , BA1 and HIGH on BA0 (The device should be in all bank
Precharge with CKE already high prior to writing into EMRS(1)). The state of address pins A0~A12 in the same cycle as CS ,
RAS , CAS , WE and BA1 going LOW and BA0 going HIGH are written in the EMRS(1).
The t_MRD time is required to complete the write operation to the EMRS(1). The EMRS(1) contents can be changed using the same
command and clock cycle requirements during normal operation as long as all banks are in the idle state. A0 is used for DLL
enable or disable. A1 is used for reducing output driver strength. The additive latency is defined by A3~A5. A7~A9 are used for
OCD control. A10 is used for
disable. ODT setting is defined by A2 and A6.
BA1 BA0
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01
Qoff
0
OCD program Rtt Additive Latency Rtt ODS DLL
A10
Enable
0
Enable
1
Disable
A6 A2 Rtt (nominal)
00
01
10
11
Disable
75 Ω
150 Ω
50 Ω
A0 DLL Enable
0
Enable
1
Disable
A1
Output Driver
Strength Control
0
Normal (100%)
1
Weak (60%)
A12
Qoff
0 Output buffer enable
1 Output buffer disable
BA1 BA0 Mode Register
0 0 MRS
0 1 EMRS(1)
1 0 EMRS(2)
1 1 EMRS(3): Reserve
Driver Impedance Adjustment
A9 A8 A7 OCD operation
0
0
0
OCD calibration
mode exit
0 0 1 Drive-1
0 1 0 Drive-0
1 0 0 Adjustable mode
1 1 1 OCD default state
Additive Latency
A5 A4 A3
000
001
010
011
100
101
110
111
Latency
0
1
2
3
4
Reverse
Reverse
Reverse
Note:
1.
2.
3.
4.
A11 and “Reserve” are reserved for future use and must be set to 0.
When adjustable mode of driver impedance is issued, the previously set value of AL must be applied.
After setting to default state of driver impedance, OCD calibration mode needs to be exited by setting A9~A7 to 000.
Qoff: the feature is intended to be used during IDD characterization of read current. When disabled, all outputs (DQs,
DQS and
) are disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
25/59